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Features
* ARM7TDMI(R) ARM(R) Thumb(R) Processor Core
- In-Circuit Emulator, 40 MHz operation
* 16-bit Fixed-point OakDSPCore(R) * * * * * * * * * * * *
- Up to 60 MHz operations - 104K bytes of Integrated Fast RAM, Codec Interface Ethernet Bridge - Dual Ethernet 10/100 Mbps MAC Interface - 16-Kbyte Frame Buffer 1 K-Byte Boot ROM, Embedding a Boot Program - Enable Application Download from DataFlash(R) External Bus Interface - On-chip 32-bit SDRAM Controller - 4 Chip Select Static Memory Controller Multi-level Priority, Individually Maskable, Vectored Interrupt Controller Three 16-bit Timer/Counters Two UARTs with Modem Control Lines Serial Peripheral Interface (SPI) Two PIO Controllers, Managing up to 48 General-purpose I/O Pins Supported by a Wide Range of Ready-to-use Application Software - Multi-tasking Operating System, Networking - Voice-processing Functions Available in a 208-lead PQFP Package and 256-ball BGA Package Power Supplies - VDDIO 3.3V nominal - VDDCORE and VDDOSC 1.8V nominal 0C to + 70C Operating Temperature Range
Smart Internet Appliance Processor (SIAPTM) AT75C221 Summary
Description
The AT75C221, Atmel's latest device in the family of smart internet appliance processors (SIAPTM), is a high-performance processor designed for professional internet appliance applications such as the Ethernet IP phone. The AT75C221 is built around an ARM7TDMI microcontroller core running at 40 MHz with an OakDSPCore coprocessor running at 60 MHz and a dual Ethernet 10/100 Mbits/sec MAC interface. In a typical standalone IP phone, the DSP handles the voice processing functions (voice compression, acoustic echo cancellation, etc.) while the dual-port Ethernet 10/100 Mbits/sec MAC interface establishes the connection to the Ethernet physical layer (PHY) that links the network and the PC. In such an application, the power of the ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control tasks. Atmel provides the AT75C221 with several software modules, including: * * A set of drivers for a Linux(R) kernel capable of driving the embedded peripherals. A comprehensive set of tunable DSP algorithms for voice processing, tailored to be run by the DSP subsystem.
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Pinout
The AT75C221 ships in two alternative packages: * * 208-lead PQFP 256-ball BGA
The product features of the 256-ball BGA package are increased compared to the 208lead PQFP package. The features available only with the BGA package are: * * * The 32-bit wide data bus (In PQFP, only a 16-bit wide data bus is supported.) The Parallel I/O lines PA13 to PA18 and PA20 to PA31 The Parallel I/O lines PB10 to PB16
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208-lead PQFP Package Pinout
Table 1. Pinout for 208-lead PQFP Package
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Signal Name
GND SCLKA VDDIO FSA STXA SRXA NTRST MA_COL MA_CRS MA_TXER MA_TXD0 MA_TXD1 MA_TXD2 MA_TXD3 MA_TXEN VDDIO MA_TXCLK GND MA_RXD0 MA_RXD1 MA_RXD2 MA_RXD3 MA_RXER MA_RXCLK GND VDDCORE MA_RXDV MA_MDC MA_MDIO MA_LINK MB_COL MB_CRS GND VDDCORE VDDIO MB_TXER
Pin Number
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Signal Name
MB_TXD0 MB_TXD1 MB_TXD2 GND MB_TXD3 MB_TXEN MB_TXCLK MB_RXD0 MB_RXD1 MB_RXD2 MB_RXD3 MB_RXER MB_RXCLK MB_RXDV MB_MDC VDDIO GND MB_MDIO MB_LINK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VDDIO GND A13 A14
Pin Number
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Signal Name
A15 A16 A17 A18 A19B/A0 A20/BA1 A21 D0 D1 D2 D3 GND D4 VDDIO D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 VDDCORE GND D15 VDDIO GND VDDIO NC
(1)
Pin Number
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Signal Name
RAS CAS NC(1) WE DQM0 DQM1 NC(1) GND NC(1) VDDCORE GND VDDOSC PLLRC GND GND XTALOUT XTALIN VDDCORE NCE0 NCE1 NCE2 VDDIO NCE3 NWE0 NWE1 NC(1) VDDIO GND NC(1) NWR NSOE GND VDDCORE VDDIO MISO MOSI
VDDIO GND SDCK SDCS SDA10
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Table 1. Pinout for 208-lead PQFP Package (Continued)
Pin Number
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Signal Name
SPCK PA22 VDDIO GND NRST FIQ IRQ0 TST GND VDDCORE NC
(1)
Pin Number
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
Signal Name
TMS TCK PA19 VDDCORE GND PA12 GND VDDIO PA11 PA10 PA9 PA8 PA7 PA6 VDDIO NC
(1)
Pin Number
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
Signal Name
PA5 PA4 PA3 PA2 PA1 PA0 GND RXDA TXDA NRSTA NCTSA NDTRA NDSRA NDCDA RXDB TXDB
Pin Number
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Signal Name
GND PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 VDDIO DBW32 GND BO256 VDDIO
VDDIO GND VDDIO TDO TDI
Note:
1. NC pins should be left unconnected.
Figure 1. 208-lead PQFP Package Orientation (Top View)
156 157 105 104
208 1 52
53
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256-ball BGA Package Pinout
Table 1. Pinout for 256-ball BGA Package
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 Signal Name GND PB9 PB4 PB1 NDSRB NRSTB RXDB NDSRA TXDA PA2 PA3 PA6 PA10 PA13 PA15 PA19 NC(1) PA23 TDO NC(1) BO256 PB8 PB7 PB3 PB0 NDTRB TXDB NDCDA NRSTA PA1 PA5 PA7 PA11 VDDCORE PA16 PA20 TMS Pin B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Signal Name TDI NC(1) NC(1) PB10 PA28 DBW32 PB6 PB2 NRIB NCTSB NRIA NCTSA PA0 PA4 PA8 PA12 PA14 PA18 PA21 TCK NC(1) NC(1) PA31 PB11 PA27 PA26 GND PB5 VDDIO NDCDB GND NDTRA RXDA VDDIO PA9 GND PA17 Pin D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 Signal Name VDDIO PA24 GND PA29 VDDCORE IRQ1 STXA FSA SCLKA PA25 PA30 TST IRQ0 NC(1) PB13 PB12 SRXA VDDIO VDDIO FIQ NC(1) SPCK MA_COL PB15 PB14 NTRST NRST PA22 MOSI MISO MA_TXD0 MA_TXER MA_CRS GND GND VDDIO VDDCORE Pin H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 Signal Name NSOE MA_TXEN MA_TXD3 MA_TXD2 MA_TXD1 NWR NWE3 NC(1) NWE2 MA_RXD0 MA_TXCLK NC(1) VDDIO NWE1 NWE0 NCE3 NCE2 MA_RXD1 MA_RXD2 MA_RXD3 MA_RXER VDDIO NCE0 NC(1) NCE1 MA_RXCLK VDDCORE MA_RXDV MA_MDC PLLRC NC(1) XTALOUT XTALIN MA_MDIO MA_LINK MB_COL GND
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Table 1. Pinout for 256-ball BGA Package (Continued)
Pin N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 Signal Name GND DQM3 VDDCORE VDDOSC MB_CRS VDDCORE MB_TXD0 MB_TXD3 RAS DQM0 DQM1 DQM2 MB_TXER MB_TXD1 MB_TXEN VDDIO VDDIO SDA10 CAS WE MB_TXD2 MB_TXCLK MB_RXD1 MB_RXER D28 D31 SDCK Pin T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 Signal Name SDCS MB_RXD0 MB_RXD2 MB_RXCLK GND A1 VDDIO A8 GND A17 VDDIO D3 D7 GND D16 VDDIO D22 GND D27 NC(1) D30 MB_RXD3 MB_RXDV NC(1) A0 A4 A7 Pin V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 Signal Name A11 A14 A18 A22 D2 D6 D10 D14 NC(1) D19 D23 D26 NC(1) D29 MB_MDC NC(1) NC(1) MB_LINK A5 A9 A12 A15 A19/BA0 A21 D1 D5 D9 Pin W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name D12 VDDCORE D17 D20 D24 VDDIO NC(1) NC(1) MB_MDIO A2 A3 A6 A10 A13 A16 A20/BA1 A23 D0 D4 D8 D11 D13 D15 D18 D21 D25 NC(1)
Note:
1. NC Balls should be left unconnected.
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Figure 2. 256-ball Package Orientation (Top View)
A B C D E F G H J K L M N P R T U V W Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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Signal Description
Table 1. Signal Description
Block Signal Name VDDIO VDDCORE Power Supplies VDDOSC GND A0-A23 External Bus Interface D0-D31 SDCK DQM0-DQM3 SDCS Synchronous Dynamic Memory Controller SDA10 RAS CAS WE BA0-BA1 NCE0-NCE3 NWE0-NWE3 Static Memory Controller NSOE NWR PIO Controller A PIO Controller B PA0-PA31 PB0-PB15 TCLK0-TCLK2 Timer Counter TIOA0-TIOA2 TIOB0-TIOA2 MISO MOSI Serial Peripheral Interface SPCK NPCS0/NSS NPCS1-NPCS3 Output Enable Memory Block Write Enable PIO Controller A I/O Lines PIO Controller B I/O Lines Timer Counter Clock 0 to 2 Timer Counter I/O Line A 0 to 2 Timer Counter I/O Line B 0 to 2 Master In/Slave Out Master Out/Slave In Serial Clock Peripheral Chip Select 0/Slave Select Peripheral Chip Select 1 to 3 Output Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Data Bus SDRAM Clock SDRAM Byte Masks SDRAM Chip Select SDRAM Address Line 10 Row Address Strobes Column Address Strobes Write Enable Bank Address Line Chip Selects Byte Select/Write Enable Input/Output Output Output Output Output Output Output Output Output Output Output PLL and Oscillator Power Supply Ground Address Bus Output Function I/O Lines Power Supply Device Core Power Supply Type
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Table 1. Signal Description (Continued)
Block Signal Name RXDA-RXDB TXDA-TXDB NRTSA-NRSTB NCTSA-NCTSB UART A and UART B NDTRA-NDTRB NDSRA-NDSRB NDCDA-NDCDB Data Terminal Ready Data Set Ready Data Carrier Detect Ring Indicator MAC A Collision Detect MAC A Carrier Sense MAC A Transmit Error MAC A Transmit Data Bus MAC A Transmit Enable MAC A Transmit Clock MAC A Receive Data Bus MAC A Receive Error MAC A Receive Clock MAC A Receive Data Valid MAC A Management Data Clock MAC A Management Data Bus MAC A Link Interrupt MAC B Collision Detect MAC B Carrier Sense MAC B Transmit Error MAC B Transmit Data Bus MAC B Transmit Enable MAC B Transmit Clock MAC B Receive Data Bus MAC B Receive Error MAC B Receive Clock MAC B Receive Data Valid MAC B Management Data Clock MAC B Management Data Bus MAC B Link Interrupt Output Input Input Input Input Input Output Output Output Input Input Input Input Output Output Input/Output Input Input Input Output Output Output Input Input Input Input Output Output Input/Output Input Function Receive Data Transmit Data Ready to Send Clear to Send Type Input Output Output Input
NRIA-NRIB
MA_COL MA_CRS MA_TXER MA_TXD0-MA_TXD3 MA_TXEN MA_TXCLK MAC A Interface MA_RXD0-MA_RXD3 MA_RXER MA_RXCLK MA_RXDV MA_MDC MA_MDIO MA_LINK MB_COL MB_CRS MB_TXER MB_TXD0-MB_TXD3 MB_TXEN MB_TXCLK MAC B Interface MB_RXD0-MB_RXD3 MB_RXER MB_RXCLK MB_RXDV MB_MDC MB_MDIO MB_LINK
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Table 1. Signal Description (Continued)
Block Signal Name NTRST TCK In-Circuit Emulator TMS TDI TDO SCLKA FSA Codec Interface STXA SRXA OAKAIN0-OAKAIN1 DSP Subsystem OAKAOUT0-OAKAOUT1 NRST FIQ IRQ0-IRQ1 PLLRC XTALIN Miscellaneous XTALOUT TST B0256 DBW32 ACLKO External Crystal Test Mode Package Size Option (1 = 256 pins) External Data Bus Width for CS0 (1 = 32 bits) ARM Clock Output Analog Input Input Input Output OakDSPCore User Output Reset Fast Interrupt Interrupt Lines PLL RC Filter Crystal Input Output Input Input Input Analog Analog Transmit Data to Codec Receive Data to Codec OakDSPCore User Input Output Input Input Function Test Reset Test Clock Test Mode Select Test Data Input Test Data Output Serial Clock Frame Pulse Type Input Input Input Input Output Input/Output Input/Output
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Block Diagram
Figure 3. AT75C221 Block Diagram
JTAG Debug Interface
ICE
ARM7TDMI MCU Core
Audio Codec and I/O Lines
OakDSPCore DSP Subsystem
Boot ROM
External Bus Interface MII PHY Interface Ethernet 10/100 Mbps MAC Interface
ASB/ASB Bridge
SDRAMC 16- or 32-bit data Memory Bus SMC
MII PHY Interface
Ethernet 10/100 Mbps MAC Interface
32k Bytes SRAM
Peripheral Data Controller Peripheral Bridge OSC. PLL Interrupt and Fast Interrupt Advanced Interrupt Controller USART A Serial Port
System Controller
SPI
Serial Peripherals Boot DataFlash
USART B I/O Lines PIO Controller A Timer/Counter 0 I/O Lines PIO Controller B Timer/Counter 1 Timer/Counter 2
Serial Port
PWM Signals PWM Signals PWM Signals
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Application Example
Figure 4. DSP Subsystem
Oak Program Bus 2K x 16 X-RAM
Oak Data Bus
Codec Interface 2K x 16 Y-RAM
32K x 16 Program RAM
OakDSPCore
16K x 16 Generalpurpose RAM
On-chip Emulation Module
256 x 16 Dual-port Mailbox
Bus Interface Unit
DSP Subsystem ASB
Figure 5. Application Example Overview: Standalone Ethernet Telephone
Keyboard Screen
Network
Ethernet 10/100 Mbps PHY Ethernet 10/100 Mbps PHY Speaker Phone Interface
PC Speaker Microphone Handset
Dual-port Ethernet 10/100 Mbps MAC Interface
SDRAM Controller VolP Protocol Stack
SDRAM
External Bus Interface
Voice Codec
Voice Processing
DSP Subsystem
SRAM Controller ARM7TDMI Core
Analog Front End
Flash
AT75C221
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AT75C221 Summary
Functional Description
ARM7TDMI Core
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16-bit wide and give maximum code density. Instructions operate on 8-bit, 16-bit and 32-bit data types. The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including six status registers.
DSP Subsystem
The AT75C221 DSP subsystem is composed of: * * * * * * * An OakDSPCore running at 60 MIPS 2K x 16 of X-RAM 2K x 16 of Y-RAM 16K x 16 of General Purpose Data RAM 32K x 16 of Loadable Program RAM One 256 x 16 Dual-port Mailbox One Codec Interface
The DSP subsystem is fully autonomous. The local X- and Y-RAM allows it to reach its maximum processing rate, and a local large data RAM enables complex DSP algorithms to be implemented. The large size of the loadable program RAM permits the use of functions as complex as a low bit-rate vocoder. During boot time, the ARM7TDMI core has the ability to maintain the OakDSPCore in reset state and to upload DSP code. When the OakDSPCore reverts to an active state, this code is executed. When the OakDSPCore is running the dual-port mailbox is used as the communication channel between the ARM7TDMI and the OakDSPCore. A programmable codec interface is directly connected to the OakDSPCore. It allows the connection of most industrial voice, multimedia or data codecs.
Ethernet MAC
The AT75C221 features two identical Ethernet MACs with the same attributes as follows: * * * * * * * * * Compatible with IEEE Standard 802.3 10 and 100 Mbits per Second Data Throughput Capability Full- and Half-duplex Operation Media Independent Interface to the Physical Layer Register Interface to Address, Status and Control Registers DMA Interface Interrupt Generation to Signal Receive and Transmit Completion 28-byte Transmit and 28-byte Receive FIFOs Automatic Pad and CRC Generation on Transmitted Frames
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* * *
Address Checking Logic to Recognize Four 48-bit Addresses Supports Promiscuous Mode Where All Valid Frames are Copied to Memory Supports Physical Layer Management through MDIO Interface
The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3u data frame format. The Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA management. In addition, it is interfaced through MDIO/MDC pins for PHY layer management. The Ethernet MAC transfers data in media-independent interface (MII).
Peripheral Multiplexing on PIO Lines
The AT75C221 features two PIO Controllers, PIOA and PIOB, multiplexing I/O lines of the peripheral set. The PIO Controller A manages 32 I/O lines, PA0 to PA31, but only the I/O lines PA0 to PA12 PA19 and PA22 are available in the 208-lead package. The PIO Controller B manages only 16 I/O lines, PB0 to PB15, but only the I/O lines PB0 to PB9 are available in the 208-lead package. Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O.
Power Supplies
The AT75C221 has three types of power supply pins: * VDDCORE pins power the core, including the ARM7TDMI processor, the DSP subsystem, the memories and the peripherals; voltage is between 1.65V and 1.95V, 1.8V nominal. VDDIO pins power the I/O lines, including those of the External Bus Interface and those of the peripherals; voltage is between 3.0V and 3.6V, 3.3V nominal. VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and 1.95V, 1.8V nominal.
* *
Ground pins are common to all power supplies.
System Controller
The AT75C221 features a System Controller, which takes care of and controls: * * * * The Test Mode The Reset The Clocks of the System The Chip Identifier
The System Controller manages the reset of the entire system and integrates a clock generator made up of an oscillator and a PLL.
Memory Controller
The AT75C221 architecture is made up of two Advanced System Buses, the ARM ASB and the MAC ASB. Both handle a single memory space. The ARM ASB handles the access requests of the ARM7TDMI and the PDC. It handles also the access requests coming from the MAC ASB. It connects with the External Bus Interface, the Peripheral Bridge and the Internal Memories, including the mailbox with the DSP Subsystem. It also connects with the MAC ASB. The MAC ASB handles the access requests of the DMAs of both Ethernet MACs. It also handles the access requests coming from the the ARM ASB. It connects essentially with the Frame Buffer, but also connects with the ARM ASB.
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The major advantage of this double-ASB architecture is that the Ethernet traffic does not occupy the main ASB bandwidth, ensuring that the ARM7TDMI can perform at its maximum speed while the Ethernet traffic goes through the Frame Buffer.
Boot Program
The AT75C221 can boot in several ways; including from internal boot software and a hardware connection of DataFlash. When the ARM7TDMI processor is released from reset, it basically attempts a fetch from address 0x00000000. Depending on the hardware configuration, the memory mapping can be altered and thus modify how the system boots. The Peripheral Bridge allows access to the embedded peripheral user interfaces. It is optimized for low power consumption, as it is built without usage of any clock. However, any access on the peripheral is performed in two cycles. The AT75C221 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has 16K bytes of address space allocated in the upper part of the address space.
Peripherals
PDC: Peripheral Data Controller
The AT75C221 features a six-channel Peripheral Data Controller (PDC) dedicated to the two on-chip UARTs and the SPI. One PDC channel is connected to the receiving channel and one to the transmitting channel of each UART and of the SPI. Each PDC channel operates as DMA (Direct Memory Access). The User Interface of a PDC channel is integrated in the memory space of each peripheral. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end-of-transfer signal is sent to the peripheral and is visible in the peripheral status register. This status bit might trigger an interrupt.
EBI: External Bus Interface
The External Bus Interface generates the signals which control access to external memories or peripheral devices. It contains two controllers: the SDRAM Controller and the Static Memory Controller and manages the sharing of data and address buses between both controllers. The SDRAM Controller extends the memory capabilities of a chip by providing the interface to an external 16- or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), halfword (16-bit) and word (32-bit) accesses. The maximum addressable SDRAM size is 256M bytes. The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The SDRAM Controller's function is to make the SDRAM device access protocol transparent to the user.
SDRAMC: SDRAM Controller
SMC: Static Memory Controller
The AT75C221 features a Static Memory Controller that enables interfacing with a wide range of external static memory on peripheral devices, including Flash, ROM, static RAM, and parallel peripherals. The SMC provides a glueless memory interface to external memory using common address, data bus and dedicated control signals. The SMC is highly programmable and 15
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has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines. The SMC supports different access protocols allowing single clock-cycle accesses. The SMC is programmed as an internal peripheral that has a standard APB bus interface and a set of memory-mapped registers. It shares the external address and data buses with the SDMC.
AIC: Advanced Interrupt Controller
The AT75C221 integrates an Advanced Interrupt Controller (AIC) which is connected to the fast interrupt request (nFIQ) and the standard interrupt request (nIRQ) inputs of the ARM7TDMI processor. The processor's nFIQ line can only be asserted by the external fast interrupt request input (FIQ). The nIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the two external interrupt request lines, IRQ0 to IRQ1. An 8-level priority encoder allows the user to define the priority between the different interrupt sources. Internal sources are programmed to be level-sensitive or edge-triggered. External sources can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive.
PIO: Programmable I/O Controller
The AT75C221 integrates 24 programmable I/O pins. Each pin can be programmed as an input or an output. Each pin can also generate an interrupt. The programmable I/O is implemented as two blocks, called PIO A and PIO B, 32 and 16 pins each, respectively. These pins are used for several functions: * * * External I/O for internal peripherals Keypad controller function General-purpose I/O
UART: Universal Asynchronous Receiver Transmitter
The AT75C221 provides two identical full-duplex, Universal Asynchronous Receiver Transmitters as UART A and UART B. These peripherals sit on the APB bus but are also connected to the ASB bus (and hence external memory) via a dedicated DMA. The main features of the UART are: * * * * * * * * Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes Interrupt Generation Two Dedicated Peripheral Data Controller Channels 6-, 7- and 8-bit Character Length Modem Control Signals
TC: Timer/Counter
The AT75C221 features a timer/counter block which includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. Each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. Each channel drives an internal interrupt signal that can be programmed to generate processor interrupts via the AIC. The timer/counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with
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the same instruction. The Block Mode Register defines the external clock inputs for each timer/counter channel, allowing them to be chained.
SPI: Serial Peripheral Interface
The Serial Peripheral Interface circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also allows communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPI's. During a data transfer, one SPI system acts as the "master"' which controls the data flow, while the other system acts as the "slave'' which has data shifted into and out of it by the master. Different CPU's can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves), and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. The main features of the SPI are: * * * * * * * * * * * * Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals Serial Memories, such as DataFlash and 3-wire EEPROMs Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors External Coprocessors Master or Serial Peripheral Bus Interface 8- to 16-bit Programmable Data Length Per Chip Select Programmable Phase and Polarity Per Chip Select Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data Per Chip Select Programmable Delay Between Consecutive Transfers Selectable Mode Fault Detection Connection to PDC Channel Capabilities Optimizes Data Transfers One Channel for the Receiver, One Channel for the Transmitter
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Ordering Information
Table 2 below provides package ordering information for the AT75C221. Table 2. Ordering Information
Ordering Code AT75C221-Q208 AT75C221-C256 Package PQFP208 BGA256 Operating Temperature Range 0 to 70 C 0 to 70 C
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Mechanical Characteristics and Packaging Information
BGA Packaging Information
Figure 6. AT75C221 BGA Package
b
For BGA package data, see Table 3 on page 20,
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BGA Package Data
Table 3. Dimensions (mm)
Symbol A1 b aaa bbb ccc ddd eee A B D/E D1/E1 e f
.
Min 0.50 0.60
Nom 0.60 0.75 0.30 0.25 0.35 0.30 0.15
Max 0.70 0.90
1.92 0.28 26.8
2.13 0.32 27.0 24.0 1.27 8.05
2.34 0.38 27.2 24.7
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PQFP Packaging Information
Figure 7. PQFP Package Drawing
C
C
1
For package data, see Table 4, Table 5 and Table 6 on page 22.
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PQFP Package Data
Table 4. Dimensions (mm)
Symbol c c1 L L1 R2 R1 S 0.13 0.13 0.4 Tolerances of Form and Position aaa ccc 0.25 0.10 Min 0.11 0.11 0.65 0.15 0.88 1.60 REF 0.3 Nom Max 0.23 0.19 1.03
Table 5. Dimensions specific to PQFP Package (mm)
A Max 4.10 A1 Min 0.25 Min 3.20 A2 Nom 3.40 Max 3.60 Min 0.17 b Max 0.27 Min 0.17 b1 Nom 0.20 Max 0.23 D BSC 31.20 D1 BSC 28.00 E BSC 31.20 E1 BSC 28.00 e BSC 0.50 ddd BSC 0.10
Table 6. 208-lead PQFP Package Electrical Characteristics
Body Size 28 x 28 R (m) Min 53 Max 71 Min 1.4 Cs (pF) Max 1.7 Min 0.56 Cm (pF) Max 0.73 Min 6.7 Ls (nH) Max 8.4 Min 3.9 Lm (nH) Max 5.1
22
AT75C221 Summary
6033CS-INTAP-05/04
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6033CS-INTAP-05/04 0M

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